概要

Programmable Timing Control Hub™ for Next Gen P4™ processor

952906A - Block Diagram
952906A - Pinout
952906A - Block Diagram
952906A - Pinout
  • 3 - 0.7V current-mode differential CPU pairs
  • 10 - PCI, 3 free running, 33MHz
  • 2 - REF, 14.318MHz
  • 3 - 3V66, 66.66MHz
  • 1 - 48MHz
  • 1 - 24/48MHz
  • 2 - 25MHz @ 2.5V
  • CPU/SRC outputs cycle-cycle jitter < 125ps
  • 3V66 outputs cycle-cycle jitter < 250ps
  • PCI outputs cycle-cycle jitter < 250ps
  • CPU - AGP skew < +/- 350ps
  • AGP-PCI skew between 1~3.5ns
  • Programmable output frequency.
  • Programmable asynchronous 3V66&PCI frequency.
  • Programmable output divider ratios.
  • Programmable output skew.
  • Programmable spread percentage for EMI control.
  • Watchdog timer technology to reset system if system malfunctions.
  • Programmable watch dog safe frequency.
  • Support I2C Index read/write and block read/write operations.
  • Uses external 14.318MHz reference input.

ドキュメント

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データシート
952906A Datasheet
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設計・開発

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Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    952906AFLFT
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 C Yes Reel
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