概要

The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.

9DB1933 - Block Diagram
9DB1933 - Pinout
9DB1933 - Block Diagram
9DB1933 - Pinout
  • 19 - 0.7 V current mode differential HCSL output pairs
  • 8 Selectable SMBus Addresses/Multiple devices can share the same SMBus Segment
  • 11 dedicated and 3 group OE# pins/Hardware control of the outputs
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
  • Spread spectrum compatible, tracks spreading input clock for low EMI
  • SMBus Interface, unused outputs can be disabled
  • Supports undriven differential outputs in Power Down mode for power management
  • Cycle-to-cycle jitter <50 ps
  • Output-to-output skew < 150 ps
  • PCIe Gen3 phase jitter < 1.0 ps RMS

ドキュメント

設計・開発

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Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    9DB1933AKLF
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 72 C Yes Tray
    9DB1933AKLFT
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 72 C Yes Reel
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    PCIe Clocking Architectures (Common and Separate)

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    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview

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    ブログ 2022年4月14日
    ブログ 2018年5月22日
    ニュース 2018年4月30日