概要

The 9EX21801 provides 18 output clocks for PCIe Gen2 (100MHz) or QPI (133MHz) applications. The 9EX21801 has 4 selectable SMBus addresses, and dedicated CKPWRGD/PD# and VDDA pins for easy board design. A differential CPU clock from a CK410B+ main clock generator, such as the 932S421, drives the 9EX21801. In fanout mode, the 9EX21801 provides outputs up to 400MHz.

9EX21801A - Block Diagram
9EX21801A - Pinout
9EX21801A - Block Diagram
9EX21801A - Pinout
  • DIF output cycle-to-cycle jitter < 50ps
  • DIF output-to-output skew < 150 ps
  • PCIe Gen2 compliant phase noise
  • QPI 133MHz compliant phase noise
  • Supports output clock frequencies up to 400 MHz
  • 4 Selectable SMBus addresses
  • SMBus address is independent of PLL operating mode
  • Dedicated CKPWRGD/PD# and VDDA pins ease board design
  • Available in industrial temperature range (-40°C to +85°C)

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    9EX21801AKILF
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 72 I Yes Tray
    9EX21801AKILFT
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 72 I Yes Reel
    9EX21801AKLF
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 72 C Yes Tray
    9EX21801AKLFT
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 72 C Yes Reel
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    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview