概要

9FG108 is a Synthesizer that provides 8 differential output pairs that are compliant to the Intel CK410 specification. It also provides support for PCI-Express, next generation I/O, and SATA. The part synthesizes several output frequencies from either a 14.31818 MHz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 65 ps.

  • Generates common frequencies from 14.318 MHz or 25 MHz
  • Crystal or reference input
  • 8 - 0.7 V HCSL differential output pairs
  • Supports Serial-ATA at 100 MHz
  • Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread
  • Unused inputs may be disabled in either driven or Hi- Z state for power management
  • Programmable OE Polarity
  • M/N Programming

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    9FG108EFILF
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 SSOP 48 I Yes Tube 3 サンプルを入手,
    9FG108EFILFT
    circleアクティブ
    memory
    view_in_ar
    		SSOP 48 I Yes Reel 3 3.572
    9FG108EFLF
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 SSOP 48 C Yes Tube 1 4.368 サンプルを入手,
    9FG108EFLFT
    circleアクティブ
    memory
    view_in_ar
    		SSOP 48 C Yes Reel 1 3.804
    9FG108EGILF
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TSSOP 48 I Yes Tube 1 5.276 サンプルを入手,
    9FG108EGILFT
    circleアクティブ
    memory
    view_in_ar
    		TSSOP 48 I Yes Reel 1
    9FG108EGLF
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TSSOP 48 C Yes Tube 1 4.312 サンプルを入手,
    9FG108EGLFT
    circleアクティブ
    memory
    view_in_ar
    		TSSOP 48 C Yes Reel 1 4.704
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    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview

    ニュース＆ブログ

    ブログ 2022年4月14日
    ブログ 2018年5月22日
    ニュース 2018年4月30日