概要
説明
特長
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Four low skew, low additive jitter LVDS output pairs
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Two selectable differential clock input pairs
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Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
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Maximum input clock frequency: 2GHz
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LVCMOS/LVTTL interface levels for the control input select pin
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Output skew: 20ps (maximum)
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Propagation delay: 300ps (maximum)
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Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 95fs (maximum)
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Full 2.5V supply voltage
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Lead-free (RoHS 6), 16-Lead VFQFN packaging
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-40°C to 85°C ambient operating temperature
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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![Diagram of ECAD Models](/themes/idt8/images/ecad-models.jpg)
ビデオ&トレーニング
Description
Overview of IDT's 8LSVP (LVPECL) and 8SLVD (LVDS) families of low-jitter fanout buffers from IDT. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. IDT's high-performance, low additive phase noise, differential clock fan-out buffers offer up to 2 GHz clock operation, low additive phase jitter (12kHz - 20MHz) of 50 to 100 femtoseconds RMS max, fast output rise & fall times (less than 150ps), and single and dual channel functions (dual: matched propagation delay). Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about IDT's industry-leading portfolio of fanout buffers, visit Renesas's RF Buffer page.
Transcript