Features
- 8 – 0.7V low-power HCSL-compatible output pairs
- LP-HCSL outputs with Zo = 85ohms ; save power and board space - no termination resistors required.
- Space-saving 48-pin VFQFPN package
- Fixed feedback path for 0ps input-to-output delay
- 8 OE# pins; hardware control of each output
- PLL or bypass mode; PLL can dejitter incoming clock
- 100MHz or 133MHz PLL mode operation; supports PCIe and QPI applications
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's
- Spread Spectrum Compatible; tracks spreading input clock for low EMI
- Cycle-to-cycle jitter < 50ps
- Output-to-output skew < 65 ps
- Input-to-output delay variation < 50ps
- PCIe Gen3 phase jitter < 1.0ps RMS
- QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
9ZXL0851A - Block Diagram
Description
The 9ZXL0851 is a low-power 8-output differential buffer that meets all the performance requirements of the Intel DB1200ZL specification. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 8 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 25 - 150 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 445 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 16 |
| Package Area (mm²) | 36 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 33 - 150 |
| Function | Buffer |
| Input Type | HCSL |
| Output Voltage (V) | 0.7 |
| Product Category | Processor Clock Buffers |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 6.0 x 6.0 x 0.9 | 48 | 0.4 |
Application Block Diagrams
 | AMD 4th-Gen EPYC (Genoa) Power & Timing System Complete power and timing system for AMD Genoa with SVI3, DDR5, and PCIe Gen 5/6 support. |
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Support Communities
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9ZXL0851E - PCIe 5.0 Clock diagram
Hi Team, I want to connect 8 pairs of 100MHz PCIe 5.0 clock cables between two circuit boards through an 800mm cable. Is the following solution feasible? Main board: CLOCK source ------>9QXL2001 ------------>Add in Card:9ZXL0851E------>800mm cable-------->Daught board: Device PCIe 100MHz reference clock. Thanks, Aris
Sep 22, 2025
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