The Renesas clock buffer (clock driver) portfolio includes devices with up to 27 outputs. Differential outputs such as LVPECL, LVDS, HCSL, CML, and HSTL, as well as selectable outputs, are supported for output frequencies up to 3.2GHz and single-ended LVCMOS outputs for frequencies up to 350MHz. Some buffers are available with mixed output signaling. The Renesas buffer portfolio has devices supporting supply voltages from 1.2V up to 5V and that are available in commercial and industrial temperature ranges. Fanout buffers and clock dividers are general-purpose clock building block devices that can be used in any number of applications. They are ideal for clock and signal distribution in a large variety of systems, from personal computers to consumer electronics or industrial systems, as well as high-performance networking and communications systems.
Standards
PCIe
JESD204B
Fanout Buffers (Clock Drivers)
Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. The clock buffer from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Single output clock buffers are useful for translating a clock from one signaling standard to another (e.g. LVCMOS-in to LVPECL-out). Some devices have an integrated crystal oscillator, requiring only a low cost external fundamental-mode quartz crystal. The integrated oscillator provides an extremely low phase noise reference clock to drive jitter-sensitive devices such as the clock inputs of PHYs. If the exact buffer configuration is not found in the extensive Renesas fanout buffer offerings, customers may consider devices in the Renesas clock divider or clock multiplexer portfolio that, when used in divide-by-1 mode or proper select mode, can also function as a fanout buffer.
