The VersaClock 3S programmable clock generators are designed for low power, consumer, and high performance PCI Express applications. The 5P35023 generates up to 5 output frequencies (3 Single-Ended and 2 Differential) out of a crystal or clock input. The 5P35021 generates up to 3 frequencies (1 Single-Ended and 2 Differential). The 5L35023 and 5L35021 devices are lower-power 1.8V versions of the 5Pxxxxx devices. Use the form below to configure your custom device.

Block Diagram (5P35023)

diagram

Timing Commander Configuration File Upload (optional)

Use this form to upload your Timing Commander configuration file for the 5P35021, 5P35023, 5L35021, or 5L35023. This will disable the configurator below. The datasheet addendum will be provided by Renesas after review.

Configuration File (.tcs) Uploader

Device Selection

Selects the device: 5P35021 features 1 Single-Ended and 2 Differential outputs. 5P35023 features 3 Single-Ended and 2 Differential outputs. Device
Selects the temperature / qualification grade of the device. Industrial/Automotive
Package 3x3 QFN 4x4 QFN 3x3 QFN 4x4 QFN
Differential Outputs 2 2 2 2
Single-Ended Outputs 1 3 1 3
Core VDD (V) 3.3 3.3 1.8 1.8
Supported Output Types
  • LVCMOS
  • LPHCSL
  • LVPECL
  • LVDS
  • LVCMOS
  • LPHCSL
  • LVPECL
  • LVDS
  • LVCMOS
  • LPHCSL
  • LVCMOS
  • LPHCSL

Global & Input Configuration

Selects the I2C address of the device. Up to 4 addresses are supported, enabling using more than one device on the same I2C bus. I2C address
Specifies the equivalent value of programmable internal load capacitors, adjustable in steps of 2 pF up to 8 pF. Crystal load capacitance
Selects the input clock options: Crystal resonator connected to X1 and X2 pins, Single-Ended clock input connected to X1, or Differential signal connected to CLKIN and CLKINB pins. Input clock configuration
Input frequency. Valid ranges are 1-to-125 MHz for Single-Ended and Differential clock inputs, 8-to-40 MHz if a Crystal Resonator is used. Input frequency
A single-ended copy of input frequency. Reference output

Output Configuration

SE1 output SE2 output SE3 output DIFF1 output DIFF2 output
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I2C or GPIO (if applicable). Enable/Disable
Output frequency. Refer to datasheet for valid frequency ranges. Frequency
This option activates a 32.768 kHz clock on the selected output. 32.768 kHz output
Selects the output signal type and level. Output mode LVCMOS LVCMOS LVCMOS
VDD voltage of the corresponding output. VDDO
Enables/Disables Spread Spectrum modulation and selects the type and amplitude of modulation: Center- or Down-Spread, with an amplitude ranging from 0.25% to 2% modulation. Spread spectrum

OE Pins Configuration

Output enable Output enable Global
power down		 Proactive
power saving		 Dynamic
freq. control		 Reset output
Selects the OE1 pin function. OE1
Selects the OE2 pin function. OE2
Selects the OE3 pin function. OE3

Project Information

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