Overview
Description
Support is limited to customers who have already adopted these products.
CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: Braze Seal DIP *H4H †H4Q Frit Seal DIP H1B Ceramic Flatpack H3W *CD4071, CD4072 †CD4075 Only
Features
- High-Voltage Types (20V Rating)
- CD4071BMS Quad 2-Input OR Gate
- CD4072BMS Dual 4-Input OR Gate
- CD4075BMS Triple 3-Input OR Gate
- Medium Speed Operation: tPHL, tPLH = 60ns (typ) at 10V
- 100% Tested for Quiescent Current at 20V
- Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25°C
- Standardized Symmetrical Output Characteristics
- Noise Margin (Over Full Package Temperature Range): 1V at VDD = 5V 2V at VDD = 10V 2.5V at VDD = 15V
- 5V, 10V and 15V Parametric Ratings
- Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Comparison
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 391 KB | |
| Brochure | PDF 5.02 MB | |
| Brochure | PDF 467 KB | |
| End Of Life Notice | PDF 200 KB | |
| Product Advisory | PDF 499 KB | |
| Product Change Notice | PDF 230 KB | |
| Application Note | PDF 338 KB | |
| Application Note | PDF 224 KB | |
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| SBDIP | 14 | Tube | 2.5 | 19.0 x 7.4 x 2.41 | 5962-96654 | No | 15 | -55 to +125°C | ||
| CFP | 14 | Tray | 1.3 | 9.8 x 6.5 x 0.00 | 5962-96654 | No | 15 | -55 to +125°C |
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