International Conferences
- Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, and Masato Motomura, "New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications", 2018 Symposia on VLSI Circuits, pp.41-42, June, 2018.
- Takao Toi, Noritsugu Nakamura, Taro Fujii, Toshiro Kitaoka, Katsumi Togawa, Koichiro Furuta, and Toru Awashima, "Optimizing Time and Space Multiplexed Computation in a Dynamically Reconfigurable Processor", ICFPT 2013, pp.106-111, Dec. 2013.
- Takao Toi, Toru Awashima, Masato Motomura, Hideharu Amano, "Time and Space-multiplexed Compilation Challenges for Dynamically Reconfigurable Processors", IEEE MWSCAS 2011 (Invited Talk), Aug. 2011.
- Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano, "Wire Congestion Aware Synthesis for a Dynamically Reconfigurable Processor", IEEE FPT 2010, pp.300-303, Dec. 2010.
- Masato Motomura: "STP Engine, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: Its Architecture, Tool, and System Implications", Proceeding of Cool Chips XII, pp.395-408, Apr. 2009.
- Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing, "High-level Synthesis Challenges and Solutions for a Dynamically Reconfigurable Processor", IEEE/ACM ICCAD 2006, pp.702-708, Nov. 2006.
- Masato Motomura: "A Dynamically Reconfigurable Processor Architecture", Microprocessor Forum, Oct. 2002.
Papers
- Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, and Hideharu Amano, "Iterative Synthesis Methods Estimating Programmable Wire Congestion in a Dynamically Reconfigurable Processor", IEICE Transaction on Fundamentals, Vol. E-94-A, No. 12, pp.2619-2627, Dec. 2011.
- Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, "High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor", IPSJ Trans. on System LSI Design Methodology, Vol. 3, pp.91-104 , Feb. 2010.