The 9FGV1002 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1002 provides four spread-spectrum copies of a single output frequency and two copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.
This is the evaluation board for the 9FGV1002 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the...
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Pkg. Type |
Supply Voltage (V) |
Output Impedance |
Xtal Freq (MHz) |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
Buy / Sample |
|
|---|---|---|---|---|---|---|---|---|
| Part Number | ||||||||
| VFQFPN | 3.3 | 100 | 8 - 50 | Tray | 1 | 3.583 | Get Samples, | |
| VFQFPN | 1.8 | 100 | 8 - 50 | Tray | 1 | 3.583 | Get Samples, | |
| VFQFPN | 3.3 | 85 | 8 - 50 | Tray | 1 | 3.583 | Get Samples, | |
| LGA | 3.3 | 100 | 8 - 50 | Tray | 3 | Get Samples, | ||
| LGA | 1.8 | 100 | 8 - 50 | Tray | 3 | 4.259 | Get Samples, | |
| LGA | 3.3 | 85 | 8 - 50 | Tray | 3 | 4.259 | Get Samples, | |
| VFQFPN | 3.3 | 100 | 8 - 50 | Reel | 1 | |||
| VFQFPN | 1.8 | 100 | 8 - 50 | Reel | 1 | |||
| VFQFPN | 3.3 | 85 | 8 - 50 | Reel | 1 | |||
| LGA | 3.3 | 100 | 8 - 50 | Reel | 3 | |||
| LGA | 1.8 | 100 | 50 | Reel | 3 | |||
| LGA | 3.3 | 85 | 8 - 50 | Reel | 3 | |||
| VFQFPN | 3.3 | 100 | 8 - 50 | Tray | 1 | Get Samples, | ||
| VFQFPN | 3.3 | 100 | 8 - 50 | Reel | 1 | |||
| VFQFPN | 1.8 | 100 | 8 - 50 | Tray | 1 | Get Samples, | ||
| VFQFPN | 1.8 | 100 | 8 - 50 | Reel | 1 | |||
| VFQFPN | 3.3 | 85 | 8 - 50 | Tray | 1 | Get Samples, | ||
| VFQFPN | 3.3 | 85 | 8 - 50 | Reel | 1 |
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
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