Evaluation Kit for 9FGV1002 Programmable PhiClock™ Generator
This is the evaluation board for the 9FGV1002 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the...
Overview
Description
The 9FGV1002 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1002 provides four spread-spectrum copies of a single output frequency and two copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.
Features
- PCIe Gen1–6 compliant
- PCIe Gen6 Common Clock jitter < 50fs RMS
- 276fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
- 4 programmable output pairs plus 2 LVCMOS REF outputs
- 1 integer, fractional or spread-spectrum output frequency per configuration
- 1MHz–325MHz output frequency (LVDS or LP-HCSL)
- 1MHz–200MHz output frequency (LVCMOS)
- 1.8V to 3.3V core VDD
- Individual 1.8V, 2.5V or 3.3V VDDO for each programmable output pair
- Supports HCSL, LVDS and LVCMOS I/O standards
- Supports AC-coupled LVPECL and CML logic – see AN-891
- 4 × 4 mm 24-VFQFPN and 24-LGA packages with 50MHz integrated crystal option
- Supported by Timing Commander™ software
Comparison
Applications
Design & Development
Software & Tools
Boards & Kits
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
This device is factory-configurable. Try the Custom Part Configuration Utility.
Processing table
Pkg. Type |
Supply Voltage (V) |
Output Impedance |
Xtal Freq (MHz) |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
Buy / Sample |
|
|---|---|---|---|---|---|---|---|---|
| Part Number | ||||||||
| VFQFPN | 3.3 | 100 | 8 - 50 | Tray | 1 | 3.583 | Get Samples, | |
| VFQFPN | 1.8 | 100 | 8 - 50 | Tray | 1 | 3.518 | Get Samples, | |
| VFQFPN | 3.3 | 85 | 8 - 50 | Tray | 1 | 3.583 | Get Samples, | |
| LGA | 3.3 | 100 | 8 - 50 | Tray | 3 | Get Samples, | ||
| LGA | 1.8 | 100 | 8 - 50 | Tray | 3 | 3.974 | Get Samples, | |
| LGA | 3.3 | 85 | 8 - 50 | Tray | 3 | 4.2 | Get Samples, | |
| VFQFPN | 3.3 | 100 | 8 - 50 | Reel | 1 | |||
| VFQFPN | 1.8 | 100 | 8 - 50 | Reel | 1 | |||
| VFQFPN | 3.3 | 85 | 8 - 50 | Reel | 1 | |||
| LGA | 3.3 | 100 | 8 - 50 | Reel | 3 | |||
| LGA | 1.8 | 100 | 50 | Reel | 3 | |||
| LGA | 3.3 | 85 | 8 - 50 | Reel | 3 | |||
| VFQFPN | 3.3 | 100 | 8 - 50 | Tray | 1 | Get Samples, | ||
| VFQFPN | 3.3 | 100 | 8 - 50 | Reel | 1 | |||
| VFQFPN | 1.8 | 100 | 8 - 50 | Tray | 1 | Get Samples, | ||
| VFQFPN | 1.8 | 100 | 8 - 50 | Reel | 1 | |||
| VFQFPN | 3.3 | 85 | 8 - 50 | Tray | 1 | Get Samples, | ||
| VFQFPN | 3.3 | 85 | 8 - 50 | Reel | 1 |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
- Reset button in header: Reset all filters to the page default
- Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
News & Blog Posts
| Blog Post | Apr 14, 2022 | ||
| Blog Post | Feb 7, 2019 | ||
| Blog Post | May 22, 2018 | ||
| News | Apr 30, 2018 |
