Radio synchronizers and JESD204B/C clock jitter attenuators offer industry-leading phase noise for best 4G/5G radio EVM performance, excellent close-in phase noise for enhanced Common Public Radio Interface (eCPRI) and CPRI applications, and high fanout for high-density radios.
Single-chip radio synchronization devices integrate digital PLLs (DPLLs) with a high-performance RF PLL and support PTP (Precision Timing Protocol, IEEE 1588), synchronous Ethernet, 1PPS input and output signals, and a tight phase alignment.
These devices remove virtually all noise from an input reference clock, making them suitable for the data converter reference clock generation and synchronization.
