Renesas Electronics Corporation
Search

8534-01

Obsolete

Low Skew,1-to-22 Differential-to-3.3V LVPECL Fanout Buffer

8534-01 Data Sheet

Overview

The 8534-01 is a low skew, 1-to-22 Differential-to-3.3V LVPECL Fanout Buffer. The 8534-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The 8534-01's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.

8534-01 - Block Diagram
8534-01 - Pinout
8534-01 - Block Diagram
8534-01 - Pinout
  • Twenty-two differential LVPECL outputs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • PCLK, nPCLK supports the following input levels: LVPECL, CML, SSTL
  • Maximum output frequency: 500MHz
  • Output skew: 100ps (maximum)
  • Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input
  • Additive phase jitter, RMS): 0.15ps (typical)
  • Full 3.3V supply mode
  • 0°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models