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NOTICE - The following device(s) are recommended alternatives:
8SLVD1204 - 2:4, LVDS Output Fanout Buffer, 2.5V

Overview

Description

The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100Ω. The 854105 accepts an LVCMOS/LVTTL input level and translates it to LVDS output levels. Guaranteed output and part-to-part skew characteristics make the 854105 ideal for those applications demanding well defined performance and repeatability.

Features

  • Four differential LVDS output pairs
  • One single-ended LVCMOS/LVTTL input
  • CLK can accept the following input levels: LVCMOS, LVTTL
  • Maximum output frequency: 250MHz
  • Translates single-ended input signals to LVDS levels
  • Additive phase jitter, RMS: 0.16ps (typical)
  • Output skew: 55ps (maximum)
  • Part-to-part skew: 350ps (maximum)
  • Propagation delay: 1.62ns (maximum)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Comparison

Applications

Documentation

Design & Development

Models

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Diagram of ECAD Models