Overview

The RG5R364 (Gen 3 RCD) is a registering clock driver used on DDR5 RDIMMs, LRDIMMs and NVDIMMs. It supports DDR5 server speeds up to 6400 MT/s. Its primary function is to buffer the Command Address (CA) bus, chip selects, and clock between the host controller and the DRAMs. It also creates a BCOM bus to control the data buffers for LRDIMMs.

The RG5R364 contains two separate channels with some common logic such as clocking, but otherwise operate independently of each other. Each channel has a 7-bit double data rate CA bus input, a single parity input, two chip-select inputs, produces two copies of 14-bit single data rate CA bus outputs and two copies of the chip-select outputs. The RCD has a common clock input and PLL, but produces separate clock outputs to the DRAM channels.

RG5R364 - Block Diagram
RG5R364 - Block Diagram
  • Pinout optimized DDR5 RDIMM and LRDIMM PCB layout
  • DDR5 server speeds up to 6400MT/s
  • Supports power-down modes to conserve server power
  • Supports 1-rank/2-rank DIMM configurations
  • Supports SDP, DDP, 3DS DRAM types
  • Supports up to 16Gb DRAM die
  • Provides access to internal control words for configuring device features and adapting to different RDIMM and LRDIMM system applications
  • I3C sideband access for asynchronous register access control
  • BCOM for LRDIMM data buffer control
  • Loopback and pass-through modes
  • Package: 8.7 × 13.5 mm, 240-FCBGA

Applications

  • RDIMM, LRDIMM and NVDIMM modules for Enterprise Servers
  • Memory down server motherboards

Documentation

= Featured Documentation
Type Title Date
Datasheet - Short-form
RG5R364A0C0GBY Short-Form Datasheet
PDF 105 KB
1 item

Design & Development

ECAD Models

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Product Options

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    Pkg. Type
    Lead Count (#)
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    RG5R364A0C0GBY#BC0
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    		FCCSP 240 Tray 0 to 70°C 3
    RG5R364A0C0GBY#HC0
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    		FCCSP 240 Reel 0 to 70°C 3
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