Overview

The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.

71V67602 - Block Diagram
71V67602 - Block Diagram
  • High system speed 166MHz (3.5ns clock access time)
  • LBO input selects interleaved or linear burst mode
  • Self-timed write cycle with global write control (GW), byte
  • write enable (BWE), and byte writes (BWx)
  • 3.3V core power supply
  • Power down controlled by ZZ input
  • 2.5V I/O supply (VDDQ)
  • Available in 100-pin TQFP and 119-pin BGA packages

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    Buy / Sample
    Part Number
    71V67602S150PFGI
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    memory
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    		TQFP 100 I Yes Tray 3 23.16
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