Overview

The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3557 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).

71V3557 Block Diagram - 128K x 36
71V3557 Block Diagram - 128K x 36
  • High performance system speed 100 MHz (7.5 ns Clock-to-Data Access)
  • ZBTTM Feature - No dead cycles between write and read cycles
  • Internally synchronized output buffer enable eliminates the need to control OE
  • Single R/W (READ/WRITE) control pin
  • 4-word burst capability (Interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • 3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)
  • Optional Boundary Scan JTAG Interface (IEEE 1149.1 complaint)
  • Available in 100-pin TQFP and 119-pin BGA packages

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    Buy / Sample
    Part Number
    71V3557S80PFGI
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    memory
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    Samples Available
    		 TQFP 100 I Yes Tray 3 8.672 Get Samples,
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