Features
- Supports high-performance system speed - 133MHz (4.2ns Clock-to-Data access)
- ZBT feature - No dead cycles between write and read cycles
- Internally synchronized registered outputs eliminate the need to control OE
- Single R/W (Read/Write) control pin
- Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
- 4-word burst capability (interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- Single 3.3V power supply (±5%)
- Available in a 100-pin TQFP package
Description
The 71V546 3.3V CMOS SRAM, organized as 128K x 36 bits, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V546 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.
Parameters
| Attributes | Value |
|---|---|
| Density (Kb) | 4608 |
| Bus Width (bits) | 36 |
| Core Voltage (V) | 3.3 |
| Pkg. Code | PKG100 |
| Organization | 128K x 36 |
| I/O Voltage (V) | - |
| I/O Frequency (MHz) | - |
| Temp. Range (°C) | -40 to 85°C |
| Architecture | ZBT |
| Output Type | Pipelined |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TQFP | 20.0 x 14.0 x 1.4 | 100 | 0.65 |