Overview
Description
The CD4000BMS (dual 3 plus inverter), CD4001BMS (quad 2-input), CD4002BMS (dual 4-input), and CD4025BMS (triple 3-input) NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4000BMS, CD4001BMS, CD4002BMS, and the CD4025BMS are supplied in these 14-lead outline packages: Braze Seal DIP H4X and H4Q, Frit Seal DIP H1B, and Ceramic Flatpack H3W.
Features
- High-voltage types (20V rating)
- Propagation delay time = 60ns (typ.) at CL = 50pF, VDD = 10V
- Buffered inputs and outputs
- Standard symmetrical output characteristics
- 100% tested for maximum quiescent current at 20V
- 5V, 10V and 15V parametric ratings
- Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
- Noise margin (over full package temperature range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
- Meets all requirements of JEDEC tentative standards No. 13B, "Standard Specifications for Description of "B" Series CMOS Device's
Comparison
Applications
Documentation
Featured Documentation
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Type | Title | Date |
Datasheet | PDF 404 KB | |
Brochure | PDF 5.02 MB | |
Brochure | PDF 467 KB | |
Price Increase Notice | PDF 360 KB | |
White Paper | PDF 533 KB | |
Product Advisory | PDF 499 KB | |
Product Change Notice | PDF 230 KB | |
Application Note | PDF 338 KB | |
Application Note | PDF 224 KB | |
9 items
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.