Choosing the PLL Bandwidth for Zero Delay Buffers in PCIe Timing Systems

IDT (acquired by Renesas) engineer provides a brief tutorial on why zero delay buffers (ZDBs) are offered with two different bandwidths (1 MHz and 3 MHz). The reason has to do with jitter peaking when cascading PLLs.

Presented by Ron Wade, PCI Express timing expert. 

Related Resources

• PCI Express (PCIe) Clocks