Overview
Description
The 9DB433 zero delay buffer (ZDB) supports PCIe Gen3 requirements while being backward compatible with PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from a 932S421 or 932SQ420 or equivalent main clock generator.
Features
- Four 0.7V HCSL differential output pairs
- Phase jitter: PCIe Gen3 < 1ps rms
- Phase jitter: PCIe Gen2 < 3.1ps rms
- Phase jitter: PCIe Gen1 < 86ps peak-to-peak
- Supports Zero Delay Buffer mode and Fanout mode
- Bandwidth programming available
- 33MHz to 110MHz operation in PLL mode
- 10MHz to 110MHz operation in Bypass mode
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| SSOP | 28 | I | Yes | Tube | 1 | 2.5 | Get Samples, | |
| SSOP | 28 | I | Yes | Reel | 1 | 2.961 | ||
| SSOP | 28 | C | Yes | Tube | 1 | 2.517 | Get Samples, | |
| SSOP | 28 | C | Yes | Reel | 1 | |||
| TSSOP | 28 | I | Yes | Tube | 1 | 2.828 | Get Samples, | |
| TSSOP | 28 | I | Yes | Reel | 1 | |||
| TSSOP | 28 | C | Yes | Tube | 1 | Get Samples, | ||
| TSSOP | 28 | C | Yes | Reel | 1 | 2.452 |
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Videos & Training
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
Video List
News & Blog Posts
| Blog Post | Apr 14, 2022 | ||
| Blog Post | May 22, 2018 | ||
| News | Apr 30, 2018 |
