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9DB833

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8-Output 3.3V PCIe Gen1-2-3 Zero Delay/Fanout Buffer

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9DB833 Datasheet
NOTICE - The following device(s) are recommended alternatives:
9DBL0841 - 8-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer9DBL0851 - 8-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer9ZXL0853E - 8-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection

Overview

The 9DB833 zero delay buffer (ZDB) supports PCIe Gen3 requirements while being backward compatible with PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from a 932S421 or 932SQ420 or equivalent main clock generator.

9DB833 - Block Diagram
9DB833 - Pinout
9DB833 - Block Diagram
9DB833 - Pinout
  • Eight 0.7V HCSL differential output pairs
  • Phase jitter: PCIe Gen3 < 1ps rms
  • Phase jitter: PCIe Gen2 < 3.1ps rms
  • Phase jitter: PCIe Gen1 < 86ps peak-to-peak
  • Supports Zero Delay Buffer mode and Fanout mode
  • Bandwidth programming available
  • 3 selectable SMBus Addresses
  • 50MHz to 110MHz operation in PLL mode
  • 5MHz to 166MHz operation in Bypass mode

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Diagram of ECAD Models

Videos & Training

PCIe Clocking Architectures (Common and Separate)

This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

Watch the Video Series Below

Video List
PCIe Clocking Architectures (Common and Separate)
PCIe Common Clock Architecture and its Impact on Clocking
PCIe Separate Reference without Spread Clock Architecture
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
Choosing the PLL Bandwidth for Zero Delay Buffers in PCIe Timing Systems

News & Blog Posts

Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System Blog Post Apr 14, 2022
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 22, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News Apr 30, 2018