Overview
Description
The 9FGV0431 is a 4-output very-low power clock generator for PCIe Gen 1–4 applications. The device has four output enables for clock management and supports two different spread spectrum levels in addition to spread off.
Features
- 1.8V operation; reduced power consumption
- OE# pins; support DIF power management
- LP-HCSL differential clock outputs; reduced power and board space
- Programmable slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- DIF outputs are blocked until PLL is locked; clean system start-up
- Selectable 0%, -0.25%, or -0.5% spread on DIF outputs; reduces EMI
- External 25MHz crystal; supports tight ppm with 0ppm synthesis error
- Configuration can be accomplished with strapping pins; SMBus interface is not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space-saving 5mm x 5mm 32-VFQFPN; minimal board space
- Selectable SMBus addresses; multiple devices can easily share an SMBus segment
Comparison
Applications
- PCIe Gen 1-4 clock generation
- Riser cards
- Storage
- Networking
- JBOD
- Communications
- Access points
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| VFQFPN | 32 | I | Yes | Tray | 3 | 2.004 | Get Samples, | |
| VFQFPN | 32 | I | Yes | Reel | 3 | |||
| VFQFPN | 32 | C | Yes | Tray | 3 | 1.769 | Get Samples, | |
| VFQFPN | 32 | C | Yes | Reel | 3 |
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Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
