Overview
Description
The 9FGV0441 is a 4-output very-low power clock generator for PCIe Gen 1–4 applications with integrated output terminations providing Zo = 100Ω. The device has four output enables for clock management and supports two different spread spectrum levels in addition to spread off.
Features
- Integrated terminations provide 100Ω differential Zo; reduced component count and board space
- 1.8V operation; reduced power consumption
- OE# pins; support DIF power management
- LP-HCSL differential clock outputs; reduced power and board space
- Programmable slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- DIF outputs are blocked until PLL is locked; clean system start-up
- Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
- External 25MHz crystal; supports tight ppm with 0ppm synthesis error
- Configuration can be accomplished with strapping pins; SMBus interface is not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space saving 5mm x 5mm 32-VFQFPN; minimal board space
- Selectable SMBus addresses; multiple devices can easily share an SMBus segment
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| VFQFPN | 32 | I | Yes | Tray | 3 | 1.948 | Get Samples, | |
| VFQFPN | 32 | I | Yes | Reel | 3 | 1.919 | ||
| VFQFPN | 32 | C | Yes | Tray | 3 | 1.563 | Get Samples, | |
| VFQFPN | 32 | C | Yes | Reel | 3 |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
- Reset button in header: Reset all filters to the page default
- Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
