Overview
Description
The 9FGV0631 is a member of IDT's SOC-Friendly 1.8 V Very-Low-Power PCIe clock family. The device has 6 output enables for clock management, 2 different spread spectrum levels in addition to spread off and 2 selectable SMBus addresses.
Features
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PCIe Gen1–4 compliant
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LP-HCSL outputs; save 12 resistors compared to standard PCIe devices
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54 mW typical power consumption; reduced thermal concerns
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Outputs can optionally be supplied from any voltage between 1.05 and 1.8 V; maximum power savings
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OE# pins; support DIF power management
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Programmable slew rate for each output; allows tuning for various line lengths
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Programmable output amplitude; allows tuning for various application environments
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DIF outputs blocked until PLL is locked; clean system start-up
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Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
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External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error
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Configuration can be accomplished with strapping pins; SMBus interface not required for device control
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3.3 V tolerant SMBus interface works with legacy controllers
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Space saving 5x5 mm 40-pin VFQFPN; minimal board space
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Selectable SMBus addresses; multiple devices can easily share an SMBus segment
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| VFQFPN | 40 | I | Yes | Tray | ||
| VFQFPN | 40 | I | Yes | Reel | ||
| VFQFPN | 40 | C | Yes | Tray | ||
| VFQFPN | 40 | C | Yes | Reel |
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Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
