Overview
Description
The 9QXL2000B is a 20-output very-low-additive phase jitter fanout buffer for PCIe Gen 4 and Gen 5. It offers integrated terminations for 85Ω transmission lines with individual output impedance trim and via SMBus registers.
Features
- Low-Power HCSL (LP-HCSL) 85Ω outputs eliminate 80 resistors, saving 130mm2 of area
- Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
- 8 OE# pins configurable to control up to 20 outputs
- 9 selectable SMBus addresses
- Spread spectrum compatible
- 10mm × 10mm 72-VFQFPN package
Comparison
Applications
- Servers
- Storage
- Networking
- SSDs
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| VFQFPN | 72 | I | Yes | Tray | 3 | 3.325 | Get Samples, | |
| VFQFPN | 72 | I | Yes | Reel | 3 |
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Videos & Training
PCIe Gen5 Clock Buffers
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.
Video List
