Overview
Description
The 71T75902 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround.
Features
- Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access)
- ZBTTM Feature - No dead cycles between write and read cycles
- Internally synchronized output buffer enable eliminates the need to control OE
- Single R/W (READ/WRITE) control pin
- 4-word burst capability (Interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- 2.5V power supply (±5%)
- 2.5V (±5%) I/O Supply (VDDQ)
- Power down controlled by ZZ input
- Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
- Available in 100-pin TQFP and 119-pin BGA packages
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
Buy / Sample |
|
|---|---|---|---|---|---|---|---|---|
| Part Number | ||||||||
| TQFP | 100 | I | Yes | Tray | 3 | 37.97 | Get Samples, | |
| TQFP | 100 | I | Yes | Reel | 3 | 33.15 |
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