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71V3559

Obsolete

3.3V 256K x 18 ZBT Synchronous Flow-Through SRAM w/3.3V I/O

71V3557_71V3559S/SA Data Sheet

Overview

The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3559 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).

71V3559 Block Diagram - 256K x 18
71V3559 Block Diagram - 256K x 18
  • High system speed 100 MHz (7.5 ns Clock-to-Data Access)
  • ZBTTM Feature - No dead cycles between write and read cycles
  • Internally synchronized output buffer enable eliminates the need to control OE
  • Single R/W (READ/WRITE) control pin
  • 4-word burst capability (Interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • 3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)
  • Optional Boundary Scan JTAG Interface (IEEE 1149.1 complaint)
  • Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages

Documentation

Design & Development

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