Overview

Description

The SH7750R is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation look aside buffer). The SH7750R has a 16-kbyte instruction cache and a 32-kbyte data cache. The SH7750R has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.

Comparison

Applications

Applications

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Documentation

Design & Development

Software & Tools

Software & Tools

Software title
Software type
Company
C/C++ Compiler Package for SuperH Family
C/C++ Compiler package for SuperH RISC engine Family. Simulator debugger and High-performance Embedded Workshop included.
Compiler/Assembler Renesas
MISRA C Rule Checker SQMlint
MISRA C Rule Checker (option)
Compiler/Assembler Renesas
E10A-USB HS0005KCU01H for H-UDI Interface
E10A-USB emulator not supporting AUD trace function.
Emulator Renesas
E10A-USB HS0005KCU02H for AUD Trace Function
E10A-USB emulator supporting AUD trace function.
Emulator Renesas
High-performance Embedded Workshop
Renesas integrated development environment (IDE) (for SuperH, RX, R8C, M32R, M16C, H8SX, H8S, H8, and 740 families).
IDE and Coding Tool Renesas
Simulator Debugger for SuperH Family
Simulator debugger for the SuperH RISC engine family [Support IDE : High-performance Embedded Workshop] (Note: This product is included in Compiler Package and is not available separately.)
Simulator Renesas
6 items

Software Downloads

Type Title Date
Software & Tools - Evaluation Software Log in to Download ZIP 122.72 MB 日本語
1 item

Sample Code

Models