Overview
Description
The 9SQ440 is an Intel CK440 main clock synthesizer for Intel cloud and HPC platforms, and newer Intel-based server platforms. 9SQ440 is a single-chip, PCIe Gen6 compliant, and is designed to work as a complete clock solution or in combination with DB2000Q-compliant clock buffers to provide point-to-point clocks to multiple receiving agents.
Features
- PCIe Gen6 phase jitter < 40fs rms
- 3 x 25MHz dedicated output pairs
- 7 x 100MHz dedicated output pairs with individual OE# pins
- 9 MXCLK output pairs multiplexable between 100MHz and 25MHz
- 3.3V operation
- 85Ω differential Low-Power HCSL (LP-HCSL) outputs eliminate 80 resistors, saving 130mm2 of area
- 9 selectable SMBus addresses
- Supports 0%, -0.3% and -0.5% spread-spectrum amounts
- Side-Band Interface allows real-time hardware control of all output enables
- OE# pin control of 100M[6:0] supports PCIe slot CLKREQ#
- Dedicated Platform Time input and output clocks (PFT_IN and PFT_OUT)
- 8 × 8 mm dual-row 100-VFQFPN
- -40°C to +85°C operating temperature range
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
| VFQFPN | 100 | I | Yes | Tray | 3 | 7.367 | Get Samples, | |
| VFQFPN | 100 | I | Yes | Reel | 3 | 7.12 |
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Videos & Training
This video provides a brief comparison of PCIe Gen3-6 common clock jitter filters vs. a typical 12k to 20MHz jitter filter plot. The tutorial explains what noise frequencies PCIe Gen6 is most sensitive to, and why it's important to minimize jitter in the 1MHz to 50MHz region. Presented by Ron Wade, system architect at Renesas. For more information about Renesas’ PCIe timing solutions, visit renesas.com/pcietiming
News & Blog Posts
| Blog Post | Apr 14, 2022 | ||
| Blog Post | Apr 14, 2022 | ||
| News | Feb 4, 2021 | ||
| Blog Post | May 22, 2018 | ||
| News | Apr 30, 2018 |
