Features
- < 100mW core power (at 3.3V)
- < 0.5ps RMS phase jitter (typical)
- Meets PCIe® Gen 1–4, USB 3.0, 1/10 GbE clock requirements
- Supports both crystal (8MHz – 40MHz) and external clock input (1MHz – 350MHz)
- 4 universal output pairs: LVPECL, LVDS, HCSL, or 8 LVCMOS outputs
- 4 independent frequencies with 0.001MHz – 350MHz output range
- Reference output
- 1.8V/2.5V/3.3V core and output voltages
- 2 programmable I²C addresses allowing multiple devices to be used in the same system
- Up to 4 different configuration sets in OTP non-volatile memory
- Supported by the Renesas IC Toolbox (RICBox) software tool
- Quick sampling and customization process supported by online form submission
- 4mm x 4mm 24-VFQFPN wettable flank package
- AEC-Q100 qualified
- -40°C to +105°C operating temperature range
Description
The 5P49V60 is a member of Renesas' VersaClock® 6E programmable clock generator family. The 5P49V60 is intended for automotive applications such as infotainment, dashboard, video processing, and in-vehicle networking, as well as applications based on PCI-Express or USB 3.0. The reference clock can come from one of the two redundant clock inputs. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation.
Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using the I²C interface.
Parameters
| Attributes | Value |
|---|---|
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5 |
| Outputs (#) | 5 |
| Output Type | LVCMOS, LVPECL, HCSL, LVDS |
| Output Freq Range (MHz) | 1 - 350 |
| Input Freq (MHz) | 1 - 350 |
| Inputs (#) | 2 |
| Input Type | Crystal, LVCMOS, LVPECL, LVDS, HCSL |
| Output Banks (#) | 4 |
| Core Voltage (V) | 1.8V, 2.5V, 3.3V |
| Output Voltage (V) | 1.8V, 2.5V, 3.3V |
| Product Category | VersaClock 6E |
| Selection Criteria | <700 fs RM |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 4.0 x 4.0 x 0.9 | 24 | 0.5 |
Application Block Diagrams
 | Cost-Effective Digital Cluster with 4-channel AHL and Surround View Digital clusters boost safety by centralizing info and reducing costs with AHL and efficient PMICs. |
 | Connected Android-Based Vehicle Instrument Cluster Android-based automotive cockpit with wireless connectivity and real-time displays. |
 | Communication Gateway & Integrated DVR/DMS System Integrated automotive gateway merging CoGW with DVR/DMS video processing. |
 | Automotive Cockpit System with Haptics Advanced cockpit system with next-generation haptics, BroadLED driver, and PMIC. |
 | Tire Pressure Monitoring System Low-power Bluetooth LE TPMS design with integrated PMIC for cost, size, and development time reduction. |
 | Parking Assistance System with AHL Camera Automotive parking camera system with HD analog link cuts cabling cost and maintains zero latency. |
 | Connected Gateway for Future E/E Architecture Renesas enables advanced E/E vehicle architecture with R-Car SoC, MCU, real-time tasks, and connectivity support. |
 | ADAS Front Camera System Scalable ADAS front camera system with NCAP-ready features and high-efficiency deep learning performance. |
 | High-End Cockpit & Infotainment Solution |