Overview

The 8T74S208C-01 is a high-performance differential LVDS clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase noise clocks. The 8T74S208C-01 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T74S208C-01 ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by an I²C register. On power-up, all outputs are disabled.

8T74S208C-01 - Block Diagram
8T74S208C-01 - Pin Assignment
8T74S208C-01 - Block Diagram
8T74S208C-01 - Pin Assignment
  • One differential input reference clock
  • Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
  • Integrated input termination resistors
  • Eight LVDS outputs
  • Selectable clock frequency division of ÷1, ÷2, ÷4, and ÷8
  • Maximum input clock frequency: 1GHz
  • LVCMOS interface levels for the control inputs
  • Individual output enabled/disabled by I²C interface
  • Output skew: 45ps (maximum)
  • Output rise/fall times: 370ps (maximum)
  • Low additive phase jitter, RMS: 96fs (typical)
  • Full 2.5V supply voltage
  • Outputs disabled at power-up
  • Lead-free (RoHS 6) 32-lead VFQFN packaging
  • -40 °C to 8 5°C ambient operating temperature

Documentation

Design & Development

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    8T74S208C-01NLGI
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    		VFQFPN 32 I Yes Tray 3 10.03 Get Samples,
    8T74S208C-01NLGI8
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