Overview
Description
The 841S101I is a PLL-based clock synthesizer specifically designed for PCI_Express™ Clock applications. This device generates a 100MHz differential HCSL clock from a input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference is applied to the XTAL_IN pin with the XTAL_OUT pin left floating.The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -.5%.The 841S101I is available in a lead-free 16-Lead TSSOP package.
Features
- One 0.7V current mode differential HCSL output pair
- Crystal oscillator interface: 25MHz
- Output frequency: 100MHz
- RMS phase jitter @ 100MHz (12kHz - 20MHz): 1.23ps (typical)
- Cycle-to-cycle jitter: 20ps (maximum)
- I2C support with readback capabilities up to 400kHz
- Spread Spectrum for electromagnetic interference (EMI) reduction
- 3.3V operating supply mode
- -40°C to 85°C ambient operating temperature
- Available in a lead-free (RoHS 6) package
- PCI Express Gen 1, 2 and 3 jitter compliant
Comparison
Applications
Documentation
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Type | Title | Date |
Datasheet | PDF 448 KB | |
Overview | PDF 2.40 MB | |
Product Change Notice | PDF 611 KB | |
Product Change Notice | PDF 611 KB | |
Product Change Notice | PDF 596 KB | |
Product Change Notice | PDF 544 KB | |
Product Change Notice | PDF 663 KB | |
Product Change Notice | PDF 439 KB | |
Product Change Notice | PDF 361 KB | |
9 items
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Videos & Training
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below