Overview

The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.

9DB1233 - Block Diagram
9DB1233 - Pinout
9DB1233 - Block Diagram
9DB1233 - Pinout
  • 12 - 0.7 V current mode differential HCSL output pairs
  • 3 Selectable SMBus Addresses/Multiple devices can share the same SMBus Segment
  • 12 OE# pins/Hardware control of each output
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
  • Spread Spectrum Compatible/tracks spreading input clock for low EMI
  • SMBus Interface/unused outputs can be disabled
  • Supports undriven differential outputs in Power Down mode for power management
  • Output cycle-cycle jitter < 50 ps
  • Output-to-output skew < 50 ps
  • PCIe Gen3 phase jitter < 1.0 ps RMS
  • Pin compatible with DB1200 Yellow Cover Device

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    9DB1233AGLF
    circleObsolete
    memory
    view_in_ar
    		TSSOP 64 C Yes Tube
    9DB1233AGLFT
    circleObsolete
    memory
    view_in_ar
    		TSSOP 64 C Yes Reel
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    Videos & Training

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
    Choosing the PLL Bandwidth for Zero Delay Buffers in PCIe Timing Systems

    News & Blog Posts

    Blog Post Apr 14, 2022
    Blog Post May 22, 2018
    News Apr 30, 2018