Overview
Description
The 9FGU0441 is a member of IDT's 1.5 V Ultra-Low-Power PCIe clock family with integrated output terminations providing Zo=100 Ω. The device has 4 output enables for clock management, 2 different spread spectrum levels in addition to spread off, and 2 selectable SMBus addresses.
Features
- Direct connection to 100 ohm transmission lines; saves 16 resistors compared to standard PCIe devices
- 39 mW typical power consumption; reduced thermal concerns
- OE# pins; support DIF power management
- Programmable Slew rate for each output; allows tuning for various line lengths.
- Programmable output amplitude; allows tuning for various application environments.
- DIF outputs blocked until PLL is locked; clean system start-up
- Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
- External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error.
- Configuration can be accomplished with strapping pins; SMBus interface not required for device control.
- 3.3 V tolerant SMBus interface works with legacy controllers.
- Space saving 5x5 mm 32-pin VFQFPN; minimal board space
- Selectable SMBus addresses; multiple devices can easily share an SMBus segment.
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Videos & Training
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
News & Blog Posts
Blog Post | Apr 14, 2022 | ||
Blog Post | May 22, 2018 | ||
News | Apr 30, 2018 |