The 9FGV1006 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1006 provides two copies of a single integer, fractional or spread-spectrum output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.
This is the evaluation board for the 9FGV1006 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the...
This is the evaluation board for the 9FGV1006Q5 programmable PhiClockTM generator with internal 50MHz crystal. It provides a convenient way of configuring and...
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Output Type |
Output Impedance |
Supply Voltage (V) |
Xtal Freq (MHz) |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
Buy / Sample |
|
|---|---|---|---|---|---|---|---|---|
| Part Number | ||||||||
| LP-HCSL | 100 | 3.3 | 25 | Tray | 3 | Get Samples, | ||
| LP-HCSL | 100 | 3.3 | 25 | Reel | 3 | |||
| LP-HCSL | 100 | 1.8 | 25 | Tray | 3 | Get Samples, | ||
| LP-HCSL | 100 | 1.8 | 25 | Reel | 3 | |||
| LP-HCSL | 85 | 3.3 | 25 | Tray | 3 | Get Samples, | ||
| LP-HCSL | 85 | 3.3 | 25 | Reel | 3 | |||
| LP-HCSL | 100 | 3.3 | 50 | Tray | 3 | 4.821 | Get Samples, | |
| LP-HCSL | 100 | 3.3 | 50 | Reel | 3 | |||
| LP-HCSL | 100 | 1.8 | 50 | Tray | 3 | 4.821 | Get Samples, | |
| LP-HCSL | 100 | 1.8 | 50 | Reel | 3 | |||
| LP-HCSL | 85 | 3.3 | 50 | Tray | 3 | 3.799 | Get Samples, | |
| LP-HCSL | 85 | 3.3 | 50 | Reel | 3 |
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
| Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System | Blog Post | Apr 14, 2022 |
| Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility | Blog Post | Jun 14, 2019 |
| Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications | Blog Post | May 22, 2018 |
| IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices | News | Apr 30, 2018 |
