Evaluation Kit for 9FGV1006 Programmable PhiClock™ Generator
This is the evaluation board for the 9FGV1006 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the...
Overview
Description
The 9FGV1006 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1006 provides two copies of a single integer, fractional or spread-spectrum output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.
Features
- PCIe Gen 1–6 compliant
- PCIe Gen 6 Common Clock jitter < 50fs RMS
- 276fs RMS typical phase jitter at 156.25MHz (12kHz to 20MHz)
- 2 programmable output pairs plus 1 LVCMOS REF output
- 1 integer, fractional or spread-spectrum output frequency per configuration
- 1MHz to 325MHz output frequency (LVDS or LP-HCSL)
- 1MHz to 200MHz output frequency (LVCMOS)
- 1.8V to 3.3V core VDD
- Individual 1.8V, 2.5V, or 3.3V VDDO for each programmable output pair
- Supports HCSL, LVDS, and LVCMOS I/O standards
- Supports AC-coupled LVPECL and CML logic – See AN-891
- 3mm × 3mm 16-LGA packages with 50MHz integrated crystal option
- Supported by Timing Commander™ software
Comparison
Applications
Design & Development
Software & Tools
Boards & Kits
Evaluation Kit for 9FGV1006 Programmable PhiClock™ Generator with Internal 50MHz Crystal
This is the evaluation board for the 9FGV1006Q5 programmable PhiClockTM generator with internal 50MHz crystal. It provides a convenient way of configuring and...
Featured Documents:
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
This device is factory-configurable. Try the Custom Part Configuration Utility.
Processing table
Output Type |
Output Impedance |
Supply Voltage (V) |
Xtal Freq (MHz) |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
Buy / Sample |
|
|---|---|---|---|---|---|---|---|---|
| Part Number | ||||||||
| LP-HCSL | 100 | 3.3 | 25 | Tray | 3 | Get Samples, | ||
| LP-HCSL | 100 | 3.3 | 25 | Reel | 3 | |||
| LP-HCSL | 100 | 1.8 | 25 | Tray | 3 | Get Samples, | ||
| LP-HCSL | 100 | 1.8 | 25 | Reel | 3 | |||
| LP-HCSL | 85 | 3.3 | 25 | Tray | 3 | Get Samples, | ||
| LP-HCSL | 85 | 3.3 | 25 | Reel | 3 | |||
| LP-HCSL | 100 | 3.3 | 50 | Tray | 3 | Get Samples, | ||
| LP-HCSL | 100 | 3.3 | 50 | Reel | 3 | |||
| LP-HCSL | 100 | 1.8 | 50 | Tray | 3 | 4.821 | Get Samples, | |
| LP-HCSL | 100 | 1.8 | 50 | Reel | 3 | |||
| LP-HCSL | 85 | 3.3 | 50 | Tray | 3 | 3.799 | Get Samples, | |
| LP-HCSL | 85 | 3.3 | 50 | Reel | 3 |
Tips for Using This Parametric Table:
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- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
News & Blog Posts
| Blog Post | Apr 14, 2022 | ||
| Blog Post | Jun 14, 2019 | ||
| Blog Post | May 22, 2018 | ||
| News | Apr 30, 2018 |
