Industry-leading PCI Express® Clock Solutions
Renesas has been first to market in PCI Express clocking and timing since its inception:
- PCIe Gen1, Gen2, Gen3, Gen4, Gen5, Gen6, and Gen7 clocking solutions
- Very-low power PCI Express clock generator (1.8V/1.5V)
- Ultra-low power HCSL (LP-HCSL) outputs (power savings up to 85% vs. standard HCSL outputs)
- Multi-PLL clock generators
With expertise with leading CPU platforms, Renesas is in the optimal position to support all your design needs for processor clocking from personal PCs to data centers and cloud servers.
Renesas recognizes how challenging it is to balance the system needs of tightening jitter limits, restrictive BOM costs, and shrinking board space. Our clocks support diverse requirements including PCI Express, SATA, USB, SAS, DMI, QPI, Hypertransport, Ethernet, etc., and multiple socket CPU architectures.
About PCI Express Clocks
PCI Express is one of the most widely used high-performance peripheral interfaces in the world. From its origins in graphics, fields as diverse as high-performance computing, servers, storage, networking, and instrumentation have adopted PCI Express. This broad application space requires multiple PCI Express clock solutions optimized for the performance/BOM cost/board-space tradeoffs of each application. Renesas' strong partnerships with leading computing, networking, and consumer vendors and our participation in the appropriate standards bodies enable us to stay at the forefront of the market with the ideal PCI Express clock and timing solutions (PCIe clocks) for every application.
Three Basic PCIe Reference Clock Architectures
CC ArchitectureCommon Clock | SRnS ArchitectureSeparate Reference No Spread | SRIS ArchitectureSeparate Reference Independent Spread | |||||||||||
| Clock Gen | Clock Gen | Clock Gen | Clock Gen | Clock Gen | |||||||||
| Clock south | Clock south | Clock south | Clock south | Clock south | Clock south | ||||||||
| Buffer (optional) | Buffer (optional) | Buffer (optional) | Buffer (optional) | Buffer (optional) | Buffer (optional) | ||||||||
| south | south | south | south | south | south | ||||||||
| CPU/SoC | swap_horiz PCIe Data | PCIe Device | CPU/SoC | swap_horiz PCIe Data | PCIe Device | CPU/SoC | swap_horiz PCIe Data | PCIe Device | |||||
