Overview
Description
The evaluation kit supports electrical AC and DC measurements of the 8V19N850DNLGI, a fully integrated radio synchronizer and JESD204B/C clock jitter attenuator. The device on the board accepts any input frequency from 1Hz to 1GHz. Locked to a selected input, the device PLLs generate clock and SYSREF signals for converter reference frequency and data frame synchronization. The 8V19N850 supports two independent frequency domains: One generates transport network clocks, such as Ethernet frequencies at 4 outputs and the other one generates radio base station clocks at 12 outputs (ADC/DAC reference clocks and SYSREF signals). Each frequency domain uses a DPLL for frequency translation, clock filtering and jitter attenuation. The DPLLs provide a programmable bandwidth and a DCO function for real-time frequency/phase adjustment.
Features
The board has SMA connectors to relevant I/O of the device:
- 2 differential clock inputs
- 4 differential digital outputs
- 5 differential RF-PLL outputs
- 5 SYSREF outputs (JESD204B/C)
- On-board EEPROM stores startup-configuration data
- 4 GPIO controls
- Selectable output buffer voltage
- XO_DPLL and OSCI terminals can use laboratory signal generator or OCXO/TCXO/XO components and board
- Laboratory power supply connectors
- Serial port for configuration and register read out
Kit contents:
- 8V19N850 evaluation board
- User’s Guide
- Configuration software (TCP file for Timing Commander)
- Configuration example file for four build-in device settings
- Board schematic and BOM
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Manual - Development Tools | PDF 2.66 MB | |
| Guide | PDF 600 KB | |
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Design & Development
Processing table
8V19N850-EVK Preview Samples Available
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