Overview
Description
The JEDEC-compliant 4RCD0232K is a Gen 2.5 DDR4 registered clock driver (RDC) for enterprise-class server RDIMMs, LRDIMMs, and UDIMMs operating with a 1.2V supply.
Features
- JEDEC-compliant RCD
- DDR4-1600/1866/2133/2400/2667/2933/3200
- Optimized for JEDEC DDR4 2667 MT/s RDIMM, LRDIMM, and UDIMM
- Designed to be used with 4DB0232KC (DDR4 Gen 2.5 DB) and TSE2004GB2C0 (DDR4 temperature sensor)
- Supports CKE power-down operation modes
- Support quad chip select operation
- Direct dual CS mode
- Direct quadCS mode
- Encoded quad CS mode
- Pinout-optimized DDR4 RDIMM, LRDIMM, and UDIMM PCB layout
- Provides access to internal control words for configuring the device features and adapting in different RDIMM and system applications
- Available in a 253-ball dual-pitch (0.50mm/0.65mm), 15 x 20 grid, rectangular ball grid array package
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| FCCSP | 253 | C | Yes | Tray | 3 | 9.699 | Get Samples, | |
| FCCSP | 253 | I | Yes | Tray | 3 | Get Samples, | ||
| FCCSP | 253 | I | Yes | Reel | 3 | Get Samples, |
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Videos & Training
How DDR4 LRDIMMs Transcend RDIMMs in Today's Enterprise Servers
A white paper authored by IDT (acquired by Renesas) and Micron details research into memory and bandwidth for today's high-performance servers. LRDIMMS and RDIMMS traditionally have been seen as complementary, with the former targeting applications requiring deeper memory and the latter for applications requiring higher bandwidth.
The introduction of 8-gigabit DRAMS has resulted in a growing number of Internet applications benefiting from both deeper memories and higher bandwidth. This paper shows how 32 GB 2RX4 LRDIMMs transcend similar RDIMMs to meet the needs of today’s data center enterprise servers, by providing an optimal combination of deeper memory and higher data bandwidth, even at mainstream module densities.
Related Resources
Video List
