概要

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation

  • DDR3-800/1066/1333/1600/1866/2133 rate
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
  • Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
  • Supports LVCMOS switching levels on the RESET and MIRROR inputs
  • Checks priority on DIMM-independent data inputs
  • Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through
  • Supports CKE Power Down operation modes
  • Supports Quad Chip Select operation features
  • RESET input disables differential input receivers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
  • Provides access to internal control words for configuring the device features and adapting in different RDIMM and system applications
  • Latch-up performance exceeds 100mA
  • ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)

ドキュメント

= ピックアップ
分類 タイトル 日時
データシート
SSTE32882KB1 Data Sheet
PDF 1.41 MB
概要
Memory Interface Products Family Overview
PDF 515 KB
製品変更通知
PCN# : A1403-02R1 Add alternate assembly for AKG176
PDF 27 KB
製品変更通知
PCN# : A1403-02 Add alternate assembly for AKG176
PDF 33 KB
4件

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    SSTE32882KB1AKG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 CABGA 176 C Yes Tray 3 サンプルを入手,
    SSTE32882KB1AKG8
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 CABGA 176 C Yes Reel 3 サンプルを入手,
    Parametric Table tips

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