ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
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5T93GL16

廃止品

2.5V LVDS,1:16 Glitchless Clock Buffer Terabuffer™ II

以下のデバイスを代替品として推奨しております。
8530I-01 - Low Skew,1-to-16 Differential-to-3.3V LVPECL Fanout Buffer

概要

The 5T93GL16 2.5V differential clock buffer is a user-selectable differential input to sixteen LVDS outputs. The fanout from a differential input to sixteen LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T93GL16 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The 5T93GL16 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

  • Guaranteed low skew: <25ps (maximum)
  • Very low duty cycle distortion: <100ps (maximum)
  • High speed propagation delay: <2ns (maximum)
  • Up to 650MHz operation
  • Glitchless input clock switching
  • Selectable inputs
  • Hot insertable and over-voltage tolerant inputs
  • 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interfaces
  • Selectable differential inputs to sixteen LVDS outputs
  • Power-down mode
  • At power-up, FSEL should be LOW
  • 2.5V VDD
  • -40°C to 85°C ambient operating temperature
  • Available in VFQFPN package

ドキュメント

設計・開発

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