概要

The 72200 is a 256 x 8 SyncFIFO™ with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication. It has 8-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.

72200 - Block Diagram
72200 - Block Diagram
  • 10 ns read/write cycle time
  • Read and Write Clocks can be asynchronous or coincidental
  • Dual-Ported zero fall-through time architecture
  • Empty and Full flags signal FIFO status
  • Almost-Empty and Almost-Full flags set to Empty+7 and Full-7, respectively
  • Output enable puts output data bus in high-impedance state
  • Available in 28-pin 300 mil plastic DIP
  • Industrial temperature range (–40C to +85C) is available

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    72200L10TP
    circle廃止品
    memory
    view_in_ar
    		PDIP 28 C No Tube
    72200L10TPG
    circle廃止品
    memory
    view_in_ar
    		PDIP 28 C Yes Tube
    72200L15TP
    circle廃止品
    memory
    view_in_ar
    		PDIP 28 C No Tube
    72200L25TP
    circle廃止品
    memory
    view_in_ar
    		PDIP 28 C No Tube
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