概要
説明
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.
特長
- 28-bit 1:2 registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on CSGateEN and RESET inputs
- Low voltage operation: VDD = 1.7V to 1.9V
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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Processing table
| CABGA | 160 | C | No | Tray | ||
| CABGA | 160 | C | No | Reel | ||
| CABGA | 160 | C | Yes | Tray | ||
| CABGA | 160 | C | Yes | Reel |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
- Reset button in header: Reset all filters to the page default
- Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product