概要

The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
71V124 - Block Diagram
71V124 - Block Diagram
  • JEDEC revolutionary pinout (center power/GND) for reduced noise
  • Equal access and cycle times
    • Commercial: 10/12/15/20ns
    • Industrial: 10/12/15/20ns
  • One Chip Select plus one Output Enable pin
  • Inputs and outputs are LVTTL-compatible
  • Single 3.3V supply
  • Low power consumption via chip deselect
  • Available in 32-pin 300-mil and 400-mil plastic SOJ, and 32-pin Type II TSOP packages

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設計・開発

ECADモデル

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Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    71V124SA10TYG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    今すぐ購入する
    		SOJ 32 C Yes Tube 3 サンプルを入手,
    71V124SA10TYG8
    circleアクティブ
    memory
    view_in_ar
    		SOJ 32 C Yes Reel 3 2.252
    71V124SA12TYGI8
    circleアクティブ
    memory
    view_in_ar
    		SOJ 32 I Yes Reel 3 2.353
    71V124SA15TYG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    今すぐ購入する
    		SOJ 32 C Yes Tube 3 2.739 サンプルを入手,
    71V124SA15TYG8
    circleアクティブ
    memory
    view_in_ar
    今すぐ購入する
    		SOJ 32 C Yes Reel 3
    71V124SA15TYGI8
    circleアクティブ
    memory
    view_in_ar
    		SOJ 32 I Yes Reel 3 2.353
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