概要

The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65903 contain address, data-in and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.

71V65903 - Block Diagram
71V65903 - Block Diagram
  • High performance system speed - 100 MHz
  • (7.5 ns Clock-to-Data Access)
  • ZBT Feature - No dead cycles between write and read
  • cycles
  • Internally synchronized output buffer enable eliminates the need to control OE
  • Single R/W (READ/WRITE) control pin
  • 4-word burst capability (Interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • 3.3V power supply (±5%)
  • 3.3V (±5%) I/O Supply (VDDQ)
  • Power down controlled by ZZ input
  • Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    71V65903S80BQG
    circleアクティブ
    memory
    view_in_ar
    		CABGA 165 C Yes Tray 3 22.21
    71V65903S80PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 I Yes Tray 3 23.16 サンプルを入手,
    71V65903S85PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 I Yes Tray 3 23.16 サンプルを入手,
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