概要
説明
2.5V 1 to 4 differential clock distributor. Optimized for clock distribution in DDR SDRAM applications. Operating frequency: 60MHZ to 220MHz
特長
- PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications
- Spread spectrum clock compatible
- Operating frequency: 60MHz to 220MHz
- Low jitter (cycle-to-cycle): ±50ps
- Distributes one differential clock input to four differential clock outputs
- Enters low power mode and 3-state outputs when input CLK signal is less than 20MHz or PWRDWN is low
- Operates from a 2.5V supply
- Consumes <200μA quiescent current
- External feedback pins (FBIN, FBIN) are used to synchronize outputs to input clocks
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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Processing table
| TSSOP | 28 | C | No | Tube | ||
| TSSOP | 28 | C | No | Reel | ||
| TSSOP | 28 | C | Yes | Tube | ||
| TSSOP | 28 | C | Yes | Reel | ||
| TSSOP | 28 | I | Yes | Tube | ||
| TSSOP | 28 | I | Yes | Reel | ||
| TSSOP | 28 | I | No | Tube | ||
| TSSOP | 28 | I | No | Reel |
Tips for Using This Parametric Table:
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- Reset button in header: Reset all filters to the page default
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- Export button in header: Export the filtered results of the table to an Excel document
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- Hide column button in column headers: Select to hide columns in table
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- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
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- Cart icon to the right of the chip icon: Indicates that samples are available for this product