概要
説明
The IDT6V31021 is a 4-output low- power differential buffer. Each output has its own OE# pin. It has a maximum operating frequency of 167 MHz and supports all SERDES clock frequencies for Freescale QorIQ CPUs.
特長
- 4 - low power differential output pairs
- Individual OE# control of each output pair
- Low power differential outputs
- Power down mode when all OE# are high
- Industrial temperature range
- 20-pin MLF
- Output cycle-cycle jitter <15 ps additive
- Output to Output skew: <50 ps
- PCIe Gen3 additive phase jitter <0.3 ps rms
- 10.3125G / 64 additive phase jitter <100 fs rms
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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Processing table
| VFQFPN | 20 | I | Yes | Tray | 1 | 2.788 | ||
| VFQFPN | 20 | I | Yes | Reel | 1 |
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ビデオ&トレーニング
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
Video List
