概要
説明
The CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD4013B dual D-Type flip-flop. The CD4027BMS is useful in performing control, register and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high-level signal is present at either the Set or Reset input. The CD4027BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T, Frit Seal DIP H1E and Ceramic Flatpack H6W.
特長
- High-voltage type (20V rating)
- Set - Reset capability
- Static flip-flop operation - Retains state indefinitely with clock level either "High" or "Low"
- Medium-speed operation - 16MHz (typ.) clock toggle rate at 10V
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20V
- Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
- Noise margin (over full package temperature range): 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
- 5V, 10V and 15V parametric ratings
- Meets all requirements of JEDEC tentative standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
製品比較
アプリケーション
- Registers
- Counters
- Control Circuits
ドキュメント
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| 分類 | タイトル | 日時 |
| データシート | PDF 332 KB | |
| カタログ | PDF 5.02 MB | |
| カタログ | PDF 467 KB | |
| Price Increase Notice | PDF 360 KB | |
| その他資料 | ||
| Product Advisory | PDF 499 KB | |
| 製品変更通知 | PDF 230 KB | |
| アプリケーションノート | PDF 338 KB | |
| アプリケーションノート | PDF 224 KB | |
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Processing table
| CFP | Tray | 25 | 5962R9662901VXC |
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