RZ/G2 microprocessors (MPU) feature a 64-bit multi-core architecture with advanced graphics capabilities and high-bandwidth memory interfaces to enable high-performance embedded systems with enhanced human machine interfaces.
High-Performance MPUs with Advanced Graphics for Next-Generation HMI in Industrial and Building Automation
Developers using embedded controllers in Industrial Automation and Building Automation applications are demanding higher performance, higher reliability and long-term software support.
To address these demands Renesas Electronics created the RZ/G2 microprocessors which combine a powerful 64-bit multi-core architecture with advanced graphics capabilities and high-bandwidth memory interfaces to enable a new generation of systems with enhanced human machine interfaces (HMI) for factory automation, process control, building power management, and video surveillance.
Renesas supports RZ/G2 application development with an industrial-grade Linux software package, maintained for 10+ years to bring reliability, functional safety, security, and feature-richness to mission-critical systems.
RZ/G2 Product Highlights
- High Performance: 64-bit Arm®v8-A cores plus powerful graphics engine and 4K UHD video engine to offer the highest performance per dollar
- High Reliability: Built-in Error Correction Code (ECC) for internal and external memory which is essential for high-reliability mission critical systems
- Super Long Term Support for Linux: Civil Infrastructure Program (CIP) Linux offers 10+ years support
- RZ/G Linux Platform Solution: Reduce development cost and time with Renesas verified software for RZ/G MPUs
RZ/G2 Entry Class MPUs
| Product | Description | Featured Document |
|---|---|---|
| RZ/G2L | General-purpose Microprocessors with Dual-core Arm® Cortex®-A55 (1.2 GHz) CPUs and Single-core Arm® Cortex®-M33 (200 MHz) CPU, with 3D Graphics and Video CODEC Engine |  |
| RZ/G2LC | General-purpose Microprocessors with Dual-core Arm® Cortex®-A55 (1.2 GHz) CPUs and Single-core Arm® Cortex®-M33 (200 MHz) CPU, with 3D Graphics | |
| RZ/G2UL | General-purpose Microprocessors with Single-core Arm® Cortex®-A55 (1.0 GHz) CPU and Single-core Arm® Cortex®-M33 (200 MHz) CPU with 2ch Gigabit Ethernet | |
RZ/G2 Entry Class MPUs Functional Overview
| Items | RZ/G2L | RZ/G2LC | RZ/G2UL |
|---|---|---|---|
| CPU (Arm® Cortex®-A) | 1× or 2× Cortex®[email protected] L1, L3 Parity/ECC | 1× or 2× Cortex®[email protected] L1, L3 Parity/ECC | 1× Cortex®[email protected] L1, L3 Parity/ECC |
| CPU (Arm® Cortex®-M) | 1× Cortex®-M33@200MHz | 1× Cortex®-M33@200MHz | 1× Cortex®-M33@200MHz |
| DRAM I/F | 16-bit ×1ch DDR4-1600/DDR3L-1333 w/ECC | 16-bit ×1ch DDR4-1600/DDR3L-1333 w/ECC | 16-bit ×1ch DDR4-1600/DDR3L-1333 w/ECC |
| Video in | 1×MIPI CSI-2 or 1×Digital Parallel input | 1×MIPI CSI-2 | 1×MIPI CSI-2 |
| Video Codec | Support up to Full HD @30fps resolutions Encoding and Decoding: H.264 | – | – |
| 3D GFX | Arm Mali-G31 GPU @500MHz | Arm Mali-G31 GPU @500MHz | – |
| Display out | 1×MIPI DSI or 1×Digital Parallel output | 1×MIPI DSI | 1×Digital Parallel output |
| USB | USB2.0×2ch (1Host, 1Host/Function/OTG) | USB2.0×2ch (1Host, 1Host/Function/OTG) | USB2.0×2ch (1Host, 1Host/Function/OTG) |
| Gbit Ether | 2ch | 1ch | 2ch |
| CAN | 2ch (support CAN-FD) | 2ch (support CAN-FD) | 2ch (support CAN-FD) |
| 12-bit ADC | 8ch | – | 2ch |
| Package | 551-pin LFBGA, 21mm×21mm 0.8mm ball pitch 456-pin LFBGA, 15mm×15mm 0.5mm ball pitch | 361-pin LFBGA, 13mm×13mm 0.5mm ball pitch | 361-pin LFBGA, 13mm×13mm 0.5mm ball pitch |
RZ/G2 High/Middle Class MPUs
| Product | Description | Featured Document |
|---|---|---|
| RZ/G2H | Ultra-high Performance Microprocessors with Quad-core Arm® Cortex®-A57 and Quad-core Arm® Cortex®-A53 CPUs, with 3D Graphics and 4K Video Encoder/Decoder | |
| RZ/G2M | Ultra-high Performance Microprocessors with Arm® Cortex®-A57 and Arm® Cortex®-A53 CPUs, with 3D Graphics and 4K Video Encoder/Decoder | |
| RZ/G2N | Ultra-high Performance Microprocessors with Dual-core Arm® Cortex®-A57 (1.5 GHz) CPUs, with 3D Graphics and 4K Video Encoder/Decoder | |
| RZ/G2E | Ultra-high Performance Microprocessors with Dual-core Arm® Cortex®-A53 (1.2 GHz) CPUs, with 3D Graphics and Video CODEC Engine | |
RZ/G2 High/Middle Class MPUs Functional Overview
| Items | RZ/G2H | RZ/G2M | RZ/G2N | RZ/G2E |
|---|---|---|---|---|
| CPU (Arm® Cortex®-A) | 4× Cortex®[email protected] 4× Cortex®[email protected] L1, L2 Parity/ECC | 2× Cortex®[email protected] 4× Cortex®[email protected] L1, L2 Parity/ECC | 2× Cortex®[email protected] L1, L2 Parity/ECC | 2× Cortex®[email protected] L1, L2 Parity/ECC |
| CPU (Arm® Cortex®-M) | 1× Cortex®-R7@800MHz L1, TCM w/ECC | 1× Cortex®-R7@800MHz L1, TCM w/ECC | 1× Cortex®-R7@800MHz L1, TCM w/ECC | 1× Cortex®-R7@800MHz L1, TCM w/ECC |
| DRAM I/F | 32-bit ×2ch LPDDR4(3200) w/ECC | 32-bit ×2ch LPDDR4(3200) w/ECC | 32-bit ×1ch LPDDR4(3200) w/ECC | 32-bit ×1ch DDR3L(1856) w/ECC |
| Video in | 2×MIPI-CSI2, 2×Digital (RGB/YCbCr) up to 8 input image can be captured | 2×MIPI-CSI2, 2×Digital (RGB/YCbCr) up to 8 input image can be captured | 2×MIPI-CSI2, 2×Digital (RGB/YCbCr) up to 8 input image can be captured | 1×MIPI-CSI2, 1×Digital (RGB/YCbCr) up to 2 input image can be captured |
| Video Codec | Support up to 4k resolutions Decoding: H.265, Encoding and Decoding: H.264 | Support up to 4k resolutions Decoding: H.265, Encoding and Decoding: H.264 | Support up to 4k resolutions Decoding: H.265, Encoding and Decoding: H.264 | Support up to FHD resolutions Decoding: H.265, Encoding and Decoding: H.264 |
| 3D GFX | PowerVR GX6650@600MHz | PowerVR GX6250@600MHz | PowerVR GE7800@600MHz | PowerVR GE8300@600MHz |
| Display out | 1×HDMI, 1×LVDS, 1×Digital RGB | 1×HDMI, 1×LVDS, 1×Digital RGB | 1×HDMI, 1×LVDS, 1×Digital RGB | 2×LVDS or 1×LVDS, 1×Digital RGB |
| USB | USB2.0×2ch (1H, 1H/F/OTG) USB3.0/2.0×1ch (DRD) | USB2.0×2ch (1H, 1H/F/OTG) USB3.0/2.0×1ch (DRD) | USB2.0×2ch (1H, 1H/F/OTG) USB3.0/2.0×1ch (DRD) | USB2.0×1ch (H/F) USB3.0/2.0×1ch (DRD) |
| Gbit Ether | 1ch | 1ch | 1ch | 1ch |
| CAN | 2ch (support CAN-FD) | 2ch (support CAN-FD) | 2ch (support CAN-FD) | 2ch (support CAN-FD) |
| PCIe | 2ch (Rev2.0 1Lane) one of the 2ch is shared with SATA | 2ch (Rev2.0 1Lane) | 2ch (Rev2.0 1Lane) one of the 2ch is shared with SATA | 1ch (Rev2.0 1Lane) |
| SATA | 1ch (Pin Shared) | No | 1ch (Pin Shared) | No |
| Package | 1022-pin FCBGA, 29mm×29mm 0.8mm ball pitch | 1022-pin FCBGA, 29mm×29mm 0.8mm ball pitch | 1022-pin FCBGA, 29mm×29mm 0.8mm ball pitch | 552-pin FCBGA, 21mm×21mm 0.8mm ball pitch |
| Pin compatibility | Pin compatible with RZ/G2M, G2N | Pin compatible with RZ/G2H, G2N | Pin compatible with RZ/G2H, G2M | – |
ECC for High Reliability
Error correcting code (ECC) functions protect RAM against radiation-induced soft errors, a critical requirement for high-reliability systems.
- The only embedded MPUs offering ECC on all internal and external memory interfaces for all device options
- RZ/G2 L1 and L2 cache SRAM memories have built-in ECC to reduce/eliminate soft errors
- DDR3L or LPDDR4 interfaces implement ECC to protect data on external memory devices
Renesas RZ/G2 microprocessors enable a secure trusted platform through many hardware features including:
- Arm TrustZone partitioning
- Cryptographic acceleration
- Secure key generation and storage
- Secure boot
- Establishment of unique root of trust
Super Long Term Software Support
Renesas RZ/G2 microprocessors are the only embedded MPUs that meet the long-term support demands for industrial and infrastructure equipment manufacturers through the 10+ year support offered by the super long term support (SLTS) kernel maintained by the Civil Infrastructure Platform (CIP). The CIP SLTS Linux kernel supports countermeasures against vulnerability to security attacks with a long-term maintenance period of 10 years or more. This reduces Linux maintenance costs and simplifies adoption of reliable industrial-grade Linux.
Download the free Civil Infrastructure Platform white paper
Civil Infrastructure Platform (CIP) project adopted the Renesas RZ/G2M-96CE board as the ARM64 reference board for the next CIP SLTS kernel.
