概要
説明
The 72T6360 is a x36 sequential flow-control device that can independently control up to four separate external memories (DDR SDRAM) for a maximum density of 1Gb (128MB). Depth expansion mode is available for applications that require more than 1Gb of storage memory. Bus-matching feature will allow the inputs and outputs to be configured to x36, x18, or x9 bus width. This device supports industry standard DDR specifications including Samsung, Micron, and Infineon memories
特長
- 166MHz operation (6ns read/write cycle time)
- 2.5V-LVTTL or 3.3V-LVTTL configured ports
- Independent and simultaneous read and write access
- IDT Standard mode or FWFT mode of operation
- Master Reset clears all data and settings
- Partial Reset clears data, but retains programmable settings
- Depth expandable with multiple devices for densities greater than 1Gb
- Width expandable with multiple devices for bus widths greater than 36 bits
- JTAG functionality (Boundary Scan)
- Available in 324-pin PBGA package
- Industrial temperature range (-40C to +85C) is available
製品比較
アプリケーション
ドキュメント
ピックアップ
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| 分類 | タイトル | 日時 |
| データシート | PDF 771 KB | |
| 製品変更通知 | PDF 24 KB | |
| アプリケーションノート | PDF 104 KB | |
| 製品変更通知 | PDF 99 KB | |
| 製品変更通知 | PDF 729 KB | |
| 製品変更通知 | PDF 80 KB | |
| 製品変更通知 | PDF 38 KB | |
| 製品変更通知 | PDF 26 KB | |
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設計・開発
モデル
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Processing table
| PBGA | 324 | C | No | Tray | ||
| PBGA | 324 | C | Yes | Tray | ||
| PBGA | 324 | C | No | Tray | ||
| PBGA | 324 | I | No | Tray |
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